1. Field of the Invention
The present invention relates to a digital-to-analog converter (DAC), and more particularly to a DAC used in successive approximation register (SAR) analog-to-digital converters (ADCs).
2. Discussion of Related Art
Lately, SAR ADCs have been attracting attention in an area having an 8 to 16-bit resolution and a 5 to 100-MS/s conversion rate. Also, due to SAR ADCs' primary advantage of low power consumption, SAR ADCs are rising as a next-generation high-efficiency data converter.
SAR ADCs employ a method of searching for a digital output value closest to an input while fixing the input and sequentially changing a reference voltage. Thus, SAR ADCs must be able to precisely perform such a process.
FIG. 1 is a circuit diagram of a conventional ADC having a DAC.
For detailed comparison and analysis, a DAC having a 5-bit resolution will be representatively described.
Referring to FIG. 1, a SAR ADC includes a logic unit, a positive DAC PDAC, a negative DAC NDAC, and a comparator AMP.
The positive DAC PDAC and the negative DAC NDAC sample analog inputs IN and INB, receive a reference voltage according to a digital signal of the logic unit, and generate input voltages for the comparator AMP.
The comparator AMP receives the input voltages from the positive DAC PDAC and the negative DAC NDAC, compares the input voltages, and generates a “low” or “high” output signal VOUT.
The logic unit stores the output signal VOUT of the comparator AMP and uses it as a next operation control signal of the positive DAC PDAC and the negative DAC NDAC.
In other words, the positive DAC PDAC and the negative DAC NDAC generate the input voltages of the comparator AMP according to a digital signal of a previous bit applied from the logic unit.
The DACs PDAC and NDAC of FIG. 1 have the general DAC structure, which includes binary weighted capacitors.
To be specific, a most significant bit (MSB) capacitor has a capacitance C4=2*C3=4*C2=8*C1=16*C0, and a capacitor C0 at the left end is an offset compensation capacitor that can be removed.
Operation of the SAR ADC including the binary weighted capacitor DACs PDAC and NDAC of FIG. 1 will now be described. First, all capacitors are connected with the analog input IN or INB at an input sampling phase.
Thus, when sampling is finished, the analog inputs IN and INB are stored in the capacitors of the positive and negative DACs PDAC and NDAC.
Here, to reduce an offset between the DACs PDAC and NDAC occurring during the sampling, electrodes connected with the top plate of the capacitor arrays of the DACs PDAC and NDAC can be connected with each other through a switch (not shown) using a prime clock, electrodes being connected to the input terminals of the comparator AMP.
When the input analog signal is sampled in the DACs PDAC and NDAC, the logic unit sets a MSB D4 to 1 and other bits to 0 and compares the sampled values with an intermediate code (10000).
To be specific, the bottom plate of the capacitor C4 of the positive DAC PDAC corresponding to the MSB is connected with a positive reference voltage REFP, the bottom plate of the capacitor C4 of the negative DAC NDAC is connected with a negative reference voltage REFN, other capacitors are reversely connected, and then the voltage levels of the two input voltages are compared with the level of a reference voltage by the comparator AMP.
When the comparator AMP compares the input voltages with the reference voltage and outputs the “high” or “low” output signal VOUT, the logic unit determines the output signal VOUT as the final MSB D4 and stores it.
Also, the logic unit repeats a conversion operation for determining a bit D3 after the MSB D4 is determined, and determines other bits using a general successive approximation method.
Such a DAC using binary weighted capacitors requires 32 unit capacitors to have a 5-bit resolution, and a logic unit must perform a successive approximation operation six times to obtain a whole 5-bit digital signal.